The present invention relates to a pipeline system, anti more particularly to the interface system of a coprocessor which is well suited to high-speed processing of a floating-point processor that is the coprocessor of a processor.
As stated in "IEEE MICRO," pp. 44-54, 1983. 12 by way of example, in a coprocessor interface of the prior art there is a system wherein, when one instruction has ended and the next instruction has been sent, a status in the execution of the operation of the preceding instruction is brought back. Therefore, the instructions are intermittently sent to a coprocessor one by one, and the overhead of the interface is heavy.
The prior-art technique does not take into consideration the enhancement of the throughput of operations, and has the problem of a long operating time.